Search Results for "systemc"
Sort By:
Showing 48 open source projects for "systemc"
View related business solutions-
Get the most trusted enterprise browserDefend against security incidents with Chrome Enterprise. Create customizable controls, manage extensions and set proactive alerts to keep your data and employees protected without slowing down productivity.
-
MongoDB Atlas runs apps anywhereMongoDB Atlas gives you the freedom to build and run modern applications anywhere—across AWS, Azure, and Google Cloud. With global availability in over 115 regions, Atlas lets you deploy close to your users, meet compliance needs, and scale with confidence across any geography.
-
1
EDAUtils Converters
Free converters across IP-XACT Verilog VHDL Liberty SystemC
...ipxact2verilog : Tool to convert IP-XACT into Verilog module ipxactinterface2svinterface : Converts IP-XACT Bus Definition / BusInterface into System Verilog Interface verilog2lib : Create Liberty .lib library from verilog module lib2verilog : Converts Liberty .lib Cells into empty verilog modules verilog2systemc : Tool to convert Verilog into SystemC keeping the original structure as much as possible. ipxactreg2xlsreg : Converts IP-XACT Address Block file into XLSX for review and documentation purpose xls2ipxact : Creates IP-XACT Address Block file from the legacy XLS/CSV based Register Management system. -
2
time-aware-computing
Model time-dependent behavior of technical and neural computing
...Based on the idea that the transfer time between computing objects cannot be neglected aside computing time, a new, time-aware, computing paradigm has been invented. The theory is introduced in practice through producing computing objects in SystemC simulator, where those times are modeled by using delays, while working on a virtual time scale. The basic object set is extended towards imitating technical computing solutions and biological computing as well. Specialized test programs, demonstration programs and docs are included. References to the science background provided. -
3
VlibTools
Tools and libraries for use with systemc and verilog
Tool suite and libraries for developing system-c models. Tools for managing RTL projects. -
4
SystemC Network Simulation Library (SCNSL) is an extension of SystemC to allow modelling packet-based networks such as wireless networks, ethernet, fieldbus, etc. As done by basic SystemC for signals on the bus, SCNSL provides primitives to model packet trasmission, reception, contention on the channel and wireless path loss. The use of SCNSL allows the easy and complete modelling of distributed applications of networked embedded systems such as wireless sensor networks, routers, and distributed plant controllers. ...
-
Level Up Your Cyber Defense with External Threat ManagementMove beyond alerts. Gain full visibility, context, and control over your external attack surface to stay ahead of every threat.
-
5
SC_CoSiM
SC_CoSiM is a plattform which focuses on validating a full system
...Our work presented at DVCon-Europe 2018 extended the technology demonstrator from David C Black(https://github.com/dcblack/technology_demonstrator). To reference this work: A. Papagrigoriou, M.D. Grammatikakis, V. Piperaki, “A hybrid channel for co-simulation of behavioral SystemC IP with its full system prototype on FPGA”, Design Verification in Europe, Munich, Germany, October 23-25 2018, pp. 1-9. Available from http://events.dvcon.org/Europe/2018/proceedings/papers/02_3.pdf -
6
Convert C++ software programs into synthesisable Verilog using the Clang compiler frontend to parse and SystemC for intermediates.
-
7
S2CBench
Synthesizable SystemC Benchmark Suite
...You can log in to our Youtube channel to watch some videos about S2CBench and SystemC in general www.youtube.com/DARClabify or visit our labs web page at www.utdallas.edu/~schaferb/darclab To know more about the designs and why they were included in the benchmark suite you can read the following academic paper: B. Carrion Schafer and A. Mahapatra, "S2CBench:Synthesizable SystemC Benchmark Suite for High-Level Synthesis ", IEEE Embedded Systems Letters, 2014 -
8
SystemC-WMS (Wave Mixed Signal Simulator) is a class library that extends the standard SystemC kernel to allow modeling and simulation of complex systems comprising analog parts from heterogeneous domain (electrical, mechanical, thermal, ...).
-
9
S3CBench
Synthesizable Security SystemC Benchmarks for High-Level Synthesis
Open source benchmark suite of synthesizable behavioral descriptions with different types of Hardware Trojan -
Simple, Secure Domain RegistrationRegister or renew your domain and pay only what we pay. No markups, hidden fees, or surprise add-ons. Choose from over 400 TLDs (.com, .ai, .dev). Every domain is integrated with Cloudflare's industry-leading DNS, CDN, and free SSL to make your site faster and more secure. Simple, secure, at-cost domain registration.
-
10
-
11
AS2CBench
Accelerated S2CBench benchmarks
Accelerated version of the Synthesizable SystemC benchmark suite (S2CBench), mapped onto Terasic's DE1-SoC FPGA board. Testbench runs on the ARM Cortex-A processor DUT is mapped onto the programmable logic. -
12
PKtool is a SystemC/C++ environment dedicated to the power estimation for digital systems described in SystemC.
-
13
SystemCFlow
Enables flow-based monitoring of SystemC models.
Flow Package is the complete software package to enable flow-based monitoring of SystemC models. It consists of the following components: 1. Flow Library: a C++ library using which the user can create a flow-based SystemC model; 2. FLOWMONGEN tool: A C++ tool that automatically generates flow monitors from flow properties; 3. Modified SystemC kernel: A modified version of OSCI kernel to monitor flows more effectively; 4. -
14
NOCEXplore
Network-on-Chip design exploration tool based on SystemC.
NOCEXplore is a Network-on-Chip design exploration tool based on SystemC. It includes libraries and executables for easy and fast upgradeable NoC models and a set of shell scripts. The project started during the PhD of Stefano Gigli at DII of Universita' Politecnica delle Marche (http://www.dii.univpm.it/) under the supervision of Prof. Massimo Conti and contribution of several students. -
15
ArchC is an open-source architecture description language based on SystemC. Its goal is to provide designers with a tool to evaluate new ideas in processor and ISA design, memory hierarchy, etc. and other aspects of computer architecture research.
-
16
CHIMP
Tool for Assertion-based Dynamic Verification of SystemC models
CHIMP is a tool for assertion-based dynamic verification of SystemC models. The various features of CHIMP include automatic generation of monitors from temporal assertions, automatic instrumentation of the model-under-verification (MUV), and three-way communication among the MUV, the generated monitors, and the SystemC simulation kernel during the monitored execution of the instrumented MUV. Empirical results show that CHIMP puts minimal runtime overhead on the monitored execution of the MUV. ... -
17
HSOC
Heterogeneous System-on-Chip Platform
...The target users are CS/EE professionals. Some experience with SoC design methodology and SystemC (e.g. reading the SystemC user manual and/or running the examples) is required. To reference this work: M.D. Grammatikakis, A. Papagrigoriou, P. Petrakis, and G. Kornaros, "Monitoring-aware VP prototypeof heterogeneous NoC-based multicore SoCs", Digital System Design Conf. (DSD), 2013, pp. 497-504. Available from http://doi.ieeecomputersociety.org/10.1109/DSD.2013.59 This research has been co-financed through the National Project Archimedes III and is co-financed by the EU project FP7-vIrtical. -
18
-
19
SImulation of CYber PHysical Systems
Simulation framework for Cyber Physical Systems
SystemC/TLM based C++ framework for simulating Cyber-Physical Systems and Wireless Sensor Networks. -
20
NoCTweak
a Parameterizable Simulator for Early Exploration of Networks On-Chip
A networks-on-chip (NoC) simulator allows designers to early estimate performance (latency and throughput), energy efficiency (average/peak power, average energy per packet) and area of several networks on-chip configurations at different CMOS nodes. This tool is a cycle-accurate simulator and is open-source using SystemC, a C++ plugin, which is used to quickly model complex systems at a higher level but less details than RTL. NoCTweak was developed by Dr. Anh Tran and Dr. Bevan Baas at UC Davis. NoCTweak has been extended and integrated into McSim, a project developed by Dr. Abdoulaye Gamatié, Dr. Gilles Sassatelli, Dr. Manuel Selva et al. at LIRMM lab. ... -
21
ASDM-NoC
Asynchronous Spatial Division Multiplexing Router for On-Chip Networks
...Features: * 5-port router for mesh network (0 south, 1 west, 2 north, 3 east, 4 local) * The dimension order routing (XY routing) * Available flow control methods: wormhole, SDM, VC * Reconfigurable number of virtual circuits, buffer size, data width * Fully synthesizable router implementation * SystemC testbench provided Languages: * Routers are written in synthesizable SystemVerilog * Test benches are provided by SystemC Software requirements: * The open source Nangate 45nm cell library * Synopsys Design Compiler (Synthesis) * Cadence IUS -- NC Simulator (for SystemC/Verilog co-simulation) -
22
Powersim
Energy Estimation in SystemC.
Power/Energy simulation in SystemC. Powersim is a SystemC class library aimed to the calculation of power and energy consumption of hardware described at system level. To this end C++ operators are monitored and different energy models can be used for each data type. Powersim does not require any change in the application source code. Current version is 0.3.0. -
23
The Sampa library is a comprehensive C++ library and lua toolset to simulate and analyze system on chip architectures through fast cycle accurate transactional level simulation. Tags: ESL, SoC, NoC, TLM, interconnect, IP, SystemC. More on sampalib.org
-
24
We release a simulator for Network-on-Chip (NoC) based manycore systems developed using UNISIM (http://unisim.org) (SystemC CLM) during Xiongfei's study at CHiPES (http://www.chipes.ntu.edu.sg), Nanyang Technological University, Singapore.
-
25
NoCBench is a Flexible Full System Simulation Platform for Network on Chip connected System on Chip. The entire source code is covered under GPL v3. For more details see LICENSE file enclosed with source code.
