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SpinalHDL is a hardware description (HDL) framework embedded in Scala, enabling hardware designers to build digital circuits with modern programming abstractions. Instead of writing in Verilog or VHDL directly, users describe hardware components and their interconnects using Scala code and Spinal’s domain-specific library, which then emits synthesizable hardware (e.g. as Verilog). Because SpinalHDL is embedded in Scala, it allows reuse of functional abstractions, parameterization, modular composition, and higher-level constructs to manage complexity. It supports building systems at various levels—single modules, pipelines, memories, controllers, etc.—while letting the designer control timing, pipelining, and resource sharing explicitly. The generated hardware can be synthesized for FPGAs or ASIC flows, making it practical for real designs.
Features
- Embedded in Scala, enabling object-oriented and functional programming paradigms in hardware specification
- Generates VHDL and Verilog outputs for compatibility with standard EDA workflows
- Produces exactly what hardware designer requests — no extra hidden overhead or “magic” constructs
- Less verbose than traditional HDLs like VHDL or Verilog; more expressive syntax
- Free/open source; usable in industrial contexts under appropriate licensing (core under LGPL, libs under MIT)
- Strong documentation, examples, multiple build options (SBT, Gradle, Mill)
Project Samples
