Open Source C++ Electronic Design Automation (EDA) Software for Windows - Page 5

Using SystemC to develop a System On Chip system. The Design includes a MIPS CPU, Arbiter, DMA controller, SRAM controller, UART controller. This design are compatible to the IBM CoreConnect™ Architecture and the On-chip Peripheral Bus (OPB) standard.

These classes are useful for signal processing in Matlab or C++. They bring together tools and methods which may be used interchangeably for Matlab and C++. Their initial use is in conjunction with work towards my degree at UC Berkeley.

Simcas is a simple and very flexible analog simulator. SimCAS uses symbolic equations to define components and solves the net system by using a "Computer Algebra System" algorithm.

toolbox with information and programs for Computer Aided Innovation The scientific background of Skidbladnir is known as the Theory of Inventive Problem Solving; in English abbreviated as TIPS or TRIZ, in German as TRIS.

Speaker Workshop is an application for testing speaker drivers using a Windows sound card, then designing and simulating loudspeakers and enclosures and creating and optimizing crossovers.

This project is in a pre-alpha stage and is intended to give a rough idea about the final program. It does not do much more than draw pretty pictures. Hierarchical circuit layout is commonplace amongst IC designers, but Spider PCB brings hierarchical layout to the PCB industry. Not only is the schematic hierarchical, but also the layout. Ever wanted to lay out a 16-band equaliser, with 5 sound channels? Lots of copying and pasting on the PCB-side. Just imagine if you could lay out one channel of the equaliser, then go up one hierarchical level and lay out 1 sound channel, using your single-band equaliser 16 times, with the only difference being the component values. You can then go up one hierarchical level more to lay out the 5 sound channels, add some headers and a power supply circuit, and another to panellise the PCB's for production. No copying and pasting. No trouble editing a mistake later. This is the idea behind Spider PCB. For more information, read the Wiki.

SymtaP is a performance analysis tool to determine the worst case execution time for embedded real time applications.

SystemC-WMS (Wave Mixed Signal Simulator) is a class library that extends the standard SystemC kernel to allow modeling and simulation of complex systems comprising analog parts from heterogeneous domain (electrical, mechanical, thermal, ...).

This is a collection of tools and a code library to assist engineers who are developing SystemVerilog based verification environments. Components include utility libraries, scoreboard and shutdown manager implementation, register tool, etc.

Scripting Tcl interface to Qt multiplatform library

TEAL - C++ multithreaded library to verfiy verilog designs

Simulator for thermal conduction in solid material. Uses SPICE for calculations and wxWindows for providing Windows and Linux GUI.

PEP is a modelling and verification framework for parallel systems, providing a large number of different modelling languages and verification techniques (e.g. SDL, Petri nets and model checking)

Two dimensional (2D) fine mesh finite element (FE) grid editing system. Includes constrained Delaunay triangulation, and automated grid resolution changes based on local attributes. Win32 and Motif GUIs. Mature application, now going open source.

Trident is a high-level language compiler for scientific agorithms written in C that target FPGAs.

The aim of the UVE project is to create software that automatically generates a verification testbench (TB) written in SystemVerilog (SV) and integrating the UVM methodology. UVE makes the rapid development of a verification environment a simple process. The generated TB is directly able to perform random actions on the DUV (design under verification). For this UVE provides a graphical user interface, a code generator, compilation scripts and a library of verification IPs (VIP). One of the main innovations of UVE is a list of TODOs in the TB code which help in finalizing the TB. This is especially useful for developers not familiar with SV and/or UVE, but also experienced developers profit from that easy to use task list. Moreover, the graphical interface lets the user observe the structure of the generated testbench. Files can be accessed easily by double clicking on the graphical view. Simulation can be launched directly from the tool.

PROJECT IS DISCUNTINUED This project is about to contain information how to write data like boot loader into various flash devices on diffrent CPUs trough JTAG interface

VHDLC is a VHDL to C++ translator aiming at full VHDL '93 compliance. It provides the translator and supporting VHDL libraries for the target host C++ compiler.

Verilator converts synthesizable Verilog HDL modules into SystemC modules. This enables users with Verilog code to have a publicly available co-simulation environment. For all information, see http://www.veripool.com/verilator.html.

Libraries and sample code for accessing remote toolpath delivery services such as VoluMill. Although much of the code is specific to the VoluMill service, it also defines open standards for exchanging toolpath information, parameters, and geometry.

A portable loudspeaker design system supporting measurement, modeling, simulation and optimization of boxes, filters and systems.

XSpiceHDL, an XSpice-VerilogHDL co-simulator incorporates a Schematic Capture GUI, modified run-time DLL capable XSpice3f5 based engine with Berkley Sockets IPC via CodeModel & PLI 1.0/2.0(VPI) DLLs, all in C++, wxWidgets & MSVC++ 6.0.

Berenice is 3D visualasion tool for electronic printed boards design. It can take design made in Eagle or any other pcb tool and visualise, rotate, zoom, move and pick in nearly real world view.

DRESD: Dynamic Reconfigurability in Embedded Systems Design.