Search Results for "verilog-xl"
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Showing 380 open source projects for "verilog-xl"
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Lite XL
A lightweight text editor written in Lua
A lightweight, simple, fast, feature-filled, and extremely extensible text editor written in C, and Lua, adapted from lite. -
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Icarus Verilog is an open source Verilog compiler that supports the IEEE-1364 Verilog HDL including IEEE1364-2005 plus extensions.
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Fooocus
Focus on prompting and generating
Fooocus is an open-source image generation software that simplifies the process of creating images from text prompts. Built on Gradio and leveraging Stable Diffusion XL, Fooocus eliminates the need for manual parameter tweaking, allowing users to focus solely on crafting prompts. It offers a user-friendly interface with minimal setup, making advanced image synthesis accessible to a broader audience. -
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GHDL
VHDL 2008/93/87 simulator
This directory contains the sources of GHDL, the open-source analyzer, compiler, simulator and (experimental) synthesizer for VHDL, a Hardware Description Language (HDL). GHDL is not an interpreter: it allows you to analyze and elaborate sources for generating machine code from your design. Native program execution is the only way for high-speed simulation. Full support for the 1987, 1993, 2002 versions of the IEEE 1076 VHDL standard, and partial for the 2008 and 2019 revisions. By using a... -
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Open-source interpreted Verilog simulator with a feature set and performance similar to Verilog-XL. Implements all IEEE 1364-1995 features along with some Verilog-2001 features. Full support for Verilog PLIs.
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SpinalHDL
Scala based HDL
SpinalHDL is a hardware description (HDL) framework embedded in Scala, enabling hardware designers to build digital circuits with modern programming abstractions. Instead of writing in Verilog or VHDL directly, users describe hardware components and their interconnects using Scala code and Spinal’s domain-specific library, which then emits synthesizable hardware (e.g. as Verilog). Because SpinalHDL is embedded in Scala, it allows reuse of functional abstractions, parameterization, modular composition, and higher-level constructs to manage complexity. ... -
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Clash
Haskell to VHDL/Verilog/SystemVerilog compiler
...Load your designs in an interpreter and easily test all your component without needing to setup a test bench. Although Clash offers many features, you sometimes need to directly access VHDL, Verilog, or SystemVerilog directly. -
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AWS EC2 FPGA
AWS EC2 FPGA hardware and software development Kit
...AFIs are reusable, shareable and can be deployed in a scalable and secure way. Development experience leverages an optimized compiler to allow easy new accelerator development or migration of existing C/C++/openCL, Verilog/VHDL to AWS FPGA instances. Fully custom hardware development experience provides hardware developers with the tools required for developing AFIs for AWS FPGA instances. -
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JarkViewer
A lightweight, lightning-fast, and powerful image viewer
JarkViewer is a lightweight, lightning‑fast image viewer for Windows 10/11 (64‑bit) that supports a wide range of modern image formats, from traditional JPEG/PNG to newer types such as AVIF, HEIC, JPEG XL, and various RAW files. It is designed as a native portable application with fully static linking, distributed as a single executable with no separate installer, making it simple to run from any folder or removable drive. The viewer handles static images, animated formats (GIF, animated WebP/PNG/APNG/JXL/AVIF), and special “live” photo types such as iOS Live Photos (.livp) and Android Motion Photos/Micro Videos, although audio playback for live photos is not yet supported. ... -
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Thorium
High-performance, privacy-focused browser built as a fork of Chromium
Thorium is a high-performance, privacy-focused web browser built as a fork of Chromium. It is designed to deliver significantly faster browsing speeds through aggressive compiler optimizations such as SSE4.2 and AVX. These low-level enhancements allow Thorium to outperform standard Chrome and Chromium builds in responsiveness and efficiency. The browser removes much of Google’s built-in bloat to create a leaner browsing experience. Thorium also includes additional privacy features that... -
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XIVLauncher
Custom launcher for FFXIV
XIVLauncher (abbreviated as XL) is a faster launcher for our favorite critically acclaimed MMO, with various available add-ons and enhancements to the game. XIVLauncher now has a native Linux version that works on Steam Deck and Desktop Linux - no more messing around with scripts and command lines, just a few easy steps to install the game and add it to Steam, with a wine version especially tuned to XIV. -
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XLS
XLS: Accelerated HW Synthesis
...The compiler lowers DSLX into a rich intermediate representation, applies aggressive optimization and scheduling passes, and can either JIT the design for software simulation or emit Verilog for FPGA/ASIC flows. A key idea is “software-style” iteration: fast, deterministic simulation via the JIT encourages test-driven development and property checking before committing to RTL. XLS also provides tooling for pipelining, state insertion, and formal equivalence checks between different stages, giving developers confidence as designs evolve. ... -
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Icestudio
Visual editor for open FPGA boards
Visual editor for open FPGA boards. Built on top of the Icestorm project using Apio. -
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System Verilog Parser IEEE 1800 LRM
IEEE LRM compliant System Verilog Parser in Java with Python, Tcl API
This parser has been developed to help users to implement their Verilog tool/utility on the top this library. It reads RTL and populates its internal data structures. There are APIs to extract the design information from the database, there are APIs to elaborate every element of the design along with basic expression evaluation capabilities. It has been bundled as an executable JAR file along with a sample application which reads a RTL file(s), elaborates and dumps it back to show the users that they will be able to extract every bit of design information from the parsed database. ... -
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libvips
A fast image processing library with low memory needs
...It supports a large range of numeric types, from 8-bit int to 128-bit complex. Images can have any number of bands. It supports a good range of image formats, including JPEG, JPEG2000, JPEG-XL, TIFF, PNG, WebP, HEIC, AVIF, FITS, Matlab, OpenEXR, PDF, SVG, HDR, PPM / PGM / PFM, CSV, GIF, Analyze, NIfTI, DeepZoom, and OpenSlide. It can also load images via ImageMagick or GraphicsMagick, letting it work with formats like DICOM. It comes with bindings for C, C++, and the command-line. Full bindings are available for Ruby, Python, PHP, C# / .NET, Go, and Lua. -
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Sloc Cloc and Code (scc)
Sloc, Cloc and Code: scc is a very fast accurate code counter
Sloc, Cloc and Code: scc is a very fast accurate code counter with complexity calculations and COCOMO estimates written in pure Go. The tool is similar to cloc, sloccount and tokei. For counting the lines of code, blank lines, comment lines, and physical lines of source code in many programming languages. The goal is to be the fastest code counter possible, but also perform COCOMO calculations like sloccount, estimate code complexity similar to cyclomatic complexity calculators, and produce... -
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PySimpleGUI_Designer
A GUI aid for designing PySimpleGUI screens.
GUI aid for designing PySimpleGUI screens and automation of layout code for the most common PySimpleGUI elements(Excel,LibreOffice & Python). The produced layout code will be pasted to the clipboard and to the PSGText sheet. The .doc file MUST be read prior to use. Added LibreOffice version(should also run in OpenOffice): GUI aid for designing PySimpleGUI screens and automation of layout code for the most common PySimpleGUI elements, written in LibreOffice Calc Basic. The produced... -
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EDAUtils Converters
Free converters across IP-XACT Verilog VHDL Liberty SystemC
verilog2vhdl : Tool to convert Verilog into VHDL by keeping the same structure and function for ease of correlation. vhdl2verilog : Tool to convert VHDL into Verilog by keeping the same structure and function for ease of correlation verilog2ipxact :Tool to create IP-XACT Component or Design from a Verilog Module. ipxact2verilog : Tool to convert IP-XACT into Verilog module ipxactinterface2svinterface : Converts IP-XACT Bus Definition / BusInterface into System Verilog Interface verilog2lib : Create Liberty .lib library from verilog module lib2verilog : Converts Liberty .lib Cells into empty verilog modules verilog2systemc : Tool to convert Verilog into SystemC keeping the original structure as much as possible. ... -
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BSC
Bluespec Compiler (BSC)
BSC is the open source compiler toolchain for Bluespec SystemVerilog, a high-level, rule-based hardware design language. It translates Bluespec descriptions into synthesizable Verilog, letting developers bring typed, modular abstractions into mainstream FPGA/ASIC flows. The compiler performs scheduling of atomic rules, elaborates parameterized modules, and enforces interface contracts, producing predictable RTL that integrates with existing EDA tools. A companion simulator enables fast functional execution and debugging before handing designs to traditional verification and synthesis stages. ... -
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Chroma
A general purpose syntax highlighter in pure Go
As Chroma has just been released, its API is still in flux. That said, the high-level interface should not change significantly. Chroma takes source code and other structured text and converts it into syntax-highlighted HTML, ANSI-coloured text, etc. Chroma is based heavily on Pygments and includes translators for Pygments lexers and styles. ABAP, ABNF, ActionScript, ActionScript 3, Ada, Angular2, ANTLR, ApacheConf, APL, AppleScript, Arduino, Awk. PacmanConf, Perl, PHP, PHTML, Pig,... -
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...Tool to compare the interfaces ( ports, parameters, SV interfaces ) between two versions of a Verilog module or two similar modules 7. Verilog Testbench Generator 8. VHDL Testbench Generator 9. Verilog Remove Assignments 10. Verilog Find Instances or Nets 11. Clock And Reset Tree Analyzer( Alpha)
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IP-XACT 2009/2014 Platform
Smart GUI/Commandline tools to create IP-XACT( 2009/2014) files
...It has capability create Bus Definitions from scratch to populate BusDef library. One can create IP-XACT Component, Design or Registers by importing Ip in System Verilog/Verilog-95/VHDL, instantiate Bus Interfaces with proper port maps and attributes as needed. Smart GUI to create IP-XACT Registers, Memory Maps, Address Blocks for IP- has feature to import XLS or Verilog . It has Tcl/Python API support. ipxact2verilog - Generate Verilog module from IP-XACT definition ipxact2vhdlentity - Generate VHDL entity from IP-XACT Component definition verilog2ipxact - Generates IP-XACT definition from Verilog modules vhdl2ipxact - Generates IP-XACT definition from VHDL source ipxactcoherencycheckerverilog / ipxactcoherencycheckervhdl - Validates IP-XACT Component definition with RTL validateipxact - IP-XACT Linting tool -
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Fallen Kingdom - Atari XL/XE
Puzzle game with chess pieces
Defeat evil red king with your own blue chess pieces -
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Official firmware for MSX++ computers and compatibles.
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iceboy
GameBoy clone
The goal of this project is to implement a GameBoy in Verilog using the open source IceStorm tools for Lattice iCE40HX-8K FPGAs.
