Michał Żygowski

Hi Mateusz, Thank you for your response. I just managed to find this out last weekend :( It seems coreboot already locks the SMRAMC register, however there was another trap waiting for me. The D_LCK bit needs to be set with PCI I/O access instead of ECAM: https://github.com/Dasharo/coreboot/commit/c7540a73860d653988d21565b892c8427709088d Also I wish the ACM error spreadsheet be consistent with Intel datasheets, i.e. at least change DLCK to D_LCK or to SMRAMC.D_LCK in the spreadhseet. It would already...

Hi Mateusz, Thank you for your response. I just managed to find this out last weekend :( It seems coreboot already locks the SMRAMC register, however there was another trap waiting for me. The D_CLK bit needs to be set with PCI I/O access instead of ECAM: https://github.com/Dasharo/coreboot/commit/c7540a73860d653988d21565b892c8427709088d Also I wish the ACM error spreadsheet be consistent with Intel datasheets, i.e. at least change DLCK to D_LCK or to SMRAMC.D_CLK in the spreadhseet. It would already...

Hello TBOOT community, When I was trying to use TBOOT to perform Intel TXT Measured Launch with Ubuntu Linux, my platform resets right after invoking GETSEC SENTER. From the decoded error code (TXT.ERRORCODE raw value 0xc0007851) I got error class 5, major 0x1e. The ACM error spreadsheet says ERR_DLCK_CONFIG - "DLOCK bit state unexpected", but I am not sure what should be the expected state. May I get more detailed explanation how to solve this error and what the expected state of DLOCK is? Also...