1. flattenverilog : Flattens the specified verilog module by removing the hierarchies. It works both for RTL and netlist.

2. preprocessverilog : Verilog Preprocessor to resolve macros like nested `ifdef , `define

3. createhierarchy : Verilog Hierarchy Creation Tool to group a list of instances in RTL or enlist. This creates a new wrapper by encapsulating the instance

4. flatteninstances : Flattens the given list of hierarchical instances- this removes hierarchy by pulling the contents in the higher leve

5. removehierarchy : Verilog Hierarchy Removal Tool to ungroup all the instances in a given module

6. comparemoduleinterfaces - Diff module ports and parameter. Tool to compare the interfaces ( ports, parameters, SV interfaces ) between two versions of a Verilog module or two similar modules

7. Verilog Testbench Generator

8. VHDL Testbench Generator

9. Verilog Remove Assignments

10. Verilog Find Instances or Nets

11. Clock And Reset Tree Analyzer( Alpha)

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Registered

2024-01-20