VeriWell Verilog Simulator Bugs

Brought to you by: elliot00, markhummel

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# Sort A -> Z Sort Z -> A	Summary▾ Sort A -> Z Sort Z -> A	Milestone▾ Sort A -> Z Sort Z -> A Filter by Milestone	Status▾ Sort A -> Z Sort Z -> A Filter by Status	Created▾ Sort A -> Z Sort Z -> A	Updated▾ Sort A -> Z Sort Z -> A
17	Compiling on X86_64 with gcc-4.3.4 breaks veriwell	None	open	2009-11-13	2009-11-13
16	Timescale differences between modules in same simulation	None	open	2009-05-18	2009-05-18
15	Bad VCD scope output	None	open	2009-05-18	2009-05-18
14	Real value equality not accurate	None	open	2009-05-18	2009-05-18
13	Real values not output to VCD file correctly	None	open	2009-05-18	2009-05-18
12	Pulldown/pullups not outputting correct VCD results	None	open	2009-05-18	2009-05-18
2	Redeclared port error	v2.8.2	open	2005-09-17	2005-09-17

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