Fix bug in the LOGICEXP scan_gates optimizer. Some gates with an inverting output were generated with bad logic which gave incorrect simulation results.
Merge branch 'pre-master-43' into bt_dev
AC simulation of noisy resistor disregards absolute 'temp' value
It is already fixed in pre-release-43 branch on 14.2.24 and will be available in next release 43. For the second issue I will take care. Thanks
AC simulation of noisy resistor disregards absolute 'temp' value
Hi Dietmar, Not quite sure what the problem was, but I did a rebuild and blackmanharris is working now, see attached. Cheers, Diarmuid
That is fine by me, but ideally the user should be informed that Ngspice is looking at either the point spec., the interval spec., or both (and then in which order). LTspice simply refuses to process the statement, so in compatibility mode something has to be done anyway. -marcel
Again, fine with me (normally only need a few measurements). Users with a few hundred measurement statements may feel otherwise (if they ever find out there is a mistake). -marcel
It is possible to do a measurement that silently overwrites a previous one with the same name. This is possible in every programming language, overwriting a variable by the last statement. Being careful is simply required. So I will not change this.
Error: measure exper find(AT) : out of interval .measure tran exper find v(2) when v(1)=-0.4 from=1ms to=1.1ms failed! I will not fix this, as its exactly saying what is going on. In the given interval there is no such point as v(1)=-0.4. If you choose an interval fitting the requirements, you will get a result value (e.g. from=0.5ms to=0.7ms).
.MEAS fails for certain border cases
Marcel, thanks for the report. I have fixed ** there is no v(3), but we get a result: yeval2 = 0.9705079 in git branch pre-master-43.
Bug 664: Report an error if token in meas statement is not a vector and
use only magnitudes in ac noise analysis even if openvaf compiled models deliver negative noise contributions
2-port noise parameters calculated incorrectly from current correlation matrix
Fixed in actual pre-master-43.
Thanks for the speedy response! Unfortunately I also do not have access to the book... used the google preview search to find specific equation numbers but viewing is limited ;-)
Thanks for your report. But it is repaired in the actual git branch pre-master-43 with my commit 1c9f8b6 from 12.2.24: cplx Ycor = csubco(ckt->CKTYmat->d[0][0], cmultco( cdivco(tempCy->d[0][1], tempCy->d[1][1]), tempCy->d[1][0] ckt->CKTYmat->d[1][0] )); double Y11_Ycor = cmodsqr(csubco(ckt->CKTYmat->d[0][0], Ycor)); @@ -138,7 +138,7 @@ CKTspnoise(CKTcircuit ckt, int mode, int operation, Ndata data, NOISEAN* noise caddco(Y0, Ysopt)); Fmin = 1.0 + 2.0 * Rn * (Ycor.re + Ysopt.re); double Ysoptmod =...
forgot to add ckt-> before CKTYmat: ckt->CKTYmat->d[1][0]
2-port noise parameters calculated incorrectly from current correlation matrix
Thank you for the corrections Arsen Arsenović. As usually happens, the hypothesis that the compiler is at fault is quite wrong, but this time has led to correct fix: diff --git a/src/xspice/icm/dlmain.c b/src/xspice/icm/dlmain.c index bde19fcd2..401800192 100644 --- a/src/xspice/icm/dlmain.c +++ b/src/xspice/icm/dlmain.c @@ -13,6 +13,7 @@ #include <stdlib.h> #include <string.h> +#include "ngspice/config.h" #include "ngspice/cpextern.h" #include "ngspice/devdefs.h" When dlmain.c can see the configured...
In \src\include\ngspice\ifsim.h, in the definition of struct IFdevice, there is an additional #ifdef OSDI const void *registry_entry; #endif after int flags; which is not there in SPICEdev spice2poly_info = { .DEVpublic = { ... and again also the sequence differs (position of int flags; before or after the XSPICE entries (does that matter?). A test might be to compile without --enable-osdi.
In \src\include\ngspice\ifsim.h, in the definition of struct IFdevice, there is an additional #ifdef OSDI const void *registry_entry; #endif after int flags; which is not there in SPICEdev spice2poly_info = { .DEVpublic = { ... and again also the sequence differs (position of int flags; before or after the XSPICE entries (does that matter?).
An obvious question: how does that work? I found it after I decided that the warning message (treated as error) is probably the result of a compiler bug. What does the warning say? It lacks any detail, but seems to mean that the typedef SPICEdev has a different meaning in dlmain.c and the ifspec.c file output from cmpp. That is ridiculous: SPICEdev is defined once in devdefs.h, there are no conditionals in the definition and the header is included into both C files. Possibly one of the types in the...
An obvious question: how does that work? I found it after I decided that the warning message (treated as error) is probably the result of a compiler bug. What does the warning say? It lacks any detail, but seems to mean that the typedef SPICEdev has a different meaning in dlmain.c and the ifspec.c file output from cmpp. That is ridiculous: SPICEdev is defined once in devdefs.h, there are no conditionals in the definition and the header is included into both C files. It is possibly one of the types...
I have a fix, but I do not think it should be adopted: diff --git a/src/xspice/icm/dlmain.c b/src/xspice/icm/dlmain.c index bde19fcd2..7403875e8 100644 --- a/src/xspice/icm/dlmain.c +++ b/src/xspice/icm/dlmain.c @@ -14,15 +14,15 @@ #include <string.h> #include "ngspice/cpextern.h" -#include "ngspice/devdefs.h" #include "ngspice/dstring.h" #include "ngspice/dllitf.h" #include "ngspice/evtudn.h" #include "ngspice/inpdefs.h" #include "ngspice/inertial.h" -#include "cmextrn.h" #include "udnextrn.h" +typedef...
The C file is old. Show "git status". This is mine: dietmar@modsys:~/Projects/spice/ngspice$ git status Auf Branch pre-master-43 Ihr Branch ist auf demselben Stand wie 'origin/pre-master-43'. nichts zu committen, Arbeitsverzeichnis unverändert Something goes wrong with your install. Can you see my commit 8aa20cfc from 24.1.2023 with gitk? My first line in console is: ** ngspice-42+ : Circuit level simulation program Yours?
Hi Dietmar, Please find attached when I run tb_fft.sp. Same result. Also attached is that c file you wanted me to check. Regards, Diarmuid
Isn't the compiler complaining about the missing 'extern'? I also notice an extra space between '..dev' and 'spice2..', had a strange problem with that myself a few days ago.
When I look at \src\include\ngspice\devdefs.h, I find this: typedef struct SPICEdev { IFdevice DEVpublic; int (*DEVparam)(int,IFvalue*,GENinstance*,IFvalue *); /* routine to input a parameter to a device instance */ ... int (*DEVnoise)(int, int, GENmodel*,CKTcircuit*, Ndata *, double *); /* noise routine */ int (*DEVsoaCheck)(CKTcircuit*,GENmodel*); /* subroutine to call on soa check */ #ifdef CIDER void (*DEVdump)(GENmodel *, CKTcircuit *); void (*DEVacct)(GENmodel *, CKTcircuit *, FILE *); /* routines...
As the language in this discussion thread is English, and I do not know what you are posting, I will delete your post immediately.
As the language in this discussion thread is Englich, and I do not know what you are posting, I will delete your post immediately.
If the function name is changed in ifspec.ifs, even by one character, the compilation succeeds. But then the problem occurs with several of the digital code models, There should be a pattern to the behaviour, but I have not found it.
If the function name is changed in ifspec.ifs, even by one character, the compilation succeeds. But them the problem occurs with several of the digital code models, There should be a pattern to the behaviour, but I have not found it.
Thanks for the report. Do you have a recommendation how to solve the potential problem in the code?
only access to CKTkluMODE if KLU configured
Why do you want to plot them? They are constants. Ah ok, that's right. Thank you.
Build fails with LTO
EDIT: Please check your src/math/fft/fftext.c file. Can you check the attached file please. This is my output: ** ngspice-42+ : Circuit level simulation program ** Compiled with Sparse Direct Linear Solver ** The U. C. Berkeley CAD Group ** Copyright 1985-1994, Regents of the University of California. ** Copyright 2001-2023, The ngspice team. ** Please get your ngspice manual from https://ngspice.sourceforge.io/docs.html ** Please file your bug-reports at http://ngspice.sourceforge.net/bugrep.html...
Can you check the attached file please. This is my output: ** ngspice-42+ : Circuit level simulation program ** Compiled with Sparse Direct Linear Solver ** The U. C. Berkeley CAD Group ** Copyright 1985-1994, Regents of the University of California. ** Copyright 2001-2023, The ngspice team. ** Please get your ngspice manual from https://ngspice.sourceforge.io/docs.html ** Please file your bug-reports at http://ngspice.sourceforge.net/bugrep.html ** Creation Date: Thu Feb 29 15:40:42 UTC 2024 Note:...
Hi Dietmar, I am trying to run blackmanharris (for the first time since the above post). However, as per the attached window, I get a warning saying the blackmanharris window is not recognised: "Warning: unknown window type blackmanharris" However, as per the attached I am running version "pre-master 43". As per the above posts this was the version blackmanharris was included in and indeed was the version I ran back in January to verify blackmanharris was working correctly. Therefore, has something...
Add a little more information on using Verilator and fix some
I add .options seed=random to my netlist and now it is ok. I have different datas every time. But I wonder why my ngspice required that line ? We could get the result we wanted without that line in ngspice 42 on my friend's computer.
You may use ngspice-42. I have been fooled by ngspice (and your netlist). You have switched on appendwrite always, I have been looking at the first few lines and searched for a change in mc.txt, but there was no change. However ngspice has simply added the new data to the bottom of the file. So add .options seed=random to your netlist, and the simulation results will vary. You may also add a line echo data > mc.txt right after .control, to generate a new file each time.
You may use ngspice-42. I have been fooled by ngspice (and your netlist). You have switched on appendwrite always, I have been looking at the first few lines and searched for a change in mc.txt, but there was no chnage. However ngspice has simply added the new data to the bottom of the file. So add .options seed=random to your netlist, and the simulation results will vary. You may also add a line echo data > mc.txt right after .control, to generate a new file each time.
what do you mean by between 34 and 35 ? which version should ı use ?
Between ngspice-34 and ngspice-35 we have lost the capability to seed the random number generators (at least on MS Windows).
ı tried version 41, 42, 42+ but it is still same and ı shared opmacro1.sp with you
Indeed ngspice is initialized with a fixed seed number 1. So if nothing else is done, the results will always be the same. However there seems to be a bug in setting the seed value to somethging different (manually or intrinsically). I will have to check that in detail.
I am already using ngspice 42 but still the same problem persists.
But this may be the problem! The simulation with its loops is probaly much faster than 1 second. This has been handled in 70e366021 ("Generate seed numbers from a microseconds clock, not a seconds clock", 2023-11-17) So please update to ngspice-42 where this has been (hopefully) solved by the microsecond clock. Unfortunately you did not post opmacro1.sp, so we cannot run the example.
Hi, The ngspice simulation gives the same data every time I run it. I deleted all the time the file that ngspice wrote data on it but the datas are not changing. This is my code. .param vdd=1.8 vss=0 voh=1.6 vol=0.2 a0=2000 vdir=0.25 ; line 2 + fgbw=10meg fnd=10g ; line-2 continuation .incl opmacro1.sp ; line 3 x1 1 2 3 opamp ; line 4 ru2 2 5 10k ; line 5 ru3 5 3 10k ; line 6 ru1 2 4 10k ; line 7 vb 4 0 0.9 ; line 8 vi 1 4 0.2 ; line 9 .control ; line 10 repeat 200 ; line 11 define agauss(mean,sigma)...
I think that is expected: the seed for the random number is a constant. On a Unix-like system, this command should be included before the loop. It will set the seed from the system clock, so the result is different each second: setseed `date +%s` I do not know how to do that on Windows.
Hi, The ngspice simulation gives the same data every time I run it. I deleted all the time the file that ngspice wrote data on it but the datas are not changing. This is my code. .param vdd=1.8 vss=0 voh=1.6 vol=0.2 a0=2000 vdir=0.25 ; line 2 + fgbw=10meg fnd=10g ; line-2 continuation .incl opmacro1.sp ; line 3 x1 1 2 3 opamp ; line 4 ru2 2 5 10k ; line 5 ru3 5 3 10k ; line 6 ru1 2 4 10k ; line 7 vb 4 0 0.9 ; line 8 vi 1 4 0.2 ; line 9 .control ; line 10 repeat 200 ; line 11 define agauss(mean,sigma)...
Why do you want to plot them? They are constants.
Ah ok, so we can't plot them.
.MEAS fails for certain border cases
model output parameters ? You may use the show and showmod commands.
Thanks, it works for BJT instance output parameters but not for BJT model output parameters. I'm using a 2N2222 BJT model (from LTspice standard.bjt library ), so I tried .save all @2N2222[is] However after running again the simulation I get the error ngspice 30 -> save all @2N2222[is] ngspice 31 -> display Here are the vectors currently active: Title: * c:\users\test\documents\ltspicexvii\carlo\amplificatore-1.asc Name: tran4 (Transient Analysis) Date: Fri Mar 22 09:42:01 2024 @2N2222[is] : current,...
Script as plain text: $ cat tranknem20pX ng_script .control set appendwrite=0 alterparam knem20p=0.5 reset tran 10n 5u write knem20p.raw vref set appendwrite=1 alterparam knem20p=0.6 reset tran 10n 5u write knem20p.raw vref alterparam knem20p=0.7 reset tran 10n 5u write knem20p.raw vref alterparam knem20p=0.8 reset tran 10n 5u write knem20p.raw vref alterparam knem20p=0.9 reset tran 10n 5u write knem20p.raw vref alterparam knem20p=1.0 reset tran 10n 5u write knem20p.raw vref .endc
This should do it: .save all @q1[ic] @q1[ib] @q1[ie] Manual 31.5.1 for the BJT parameters and 31.1 for the syntax. "All" must be included to preserve the default list of saved values.
Lookup the 'rshunt' and 'gmin' options in the manual. However, it will still be possible to design a circuit which doesn't converge. I would give the player extra points if his circuit does not generate any warnings or errors :--) -marcel
Hi, like i already mentioned in an older topic "Unable to use XSPICE A-statements in shared ngspice.", im currently working on a game engine, that uses SPICE to simulate circuits that the player builds. I just noticed a little problem, i can't control what the user builds, and if this circuit contains unconnected nodes, it results in "singular matrix" warning, which often cause the simulation to fail. Is there some sort of flag or option i can set, to let spice just ignore nodes that re not connected...
Hi, like i already mentioned in an older topic "Unable to use XSPICE A-statements in shared ngspice.", im currently working on a game engine, that uses SPICE to simulate circuits that the player builds. I just noticed a little problem, i cant control what the user builds, and if this circuit contains unconnected nodes, it results in "singular matrix" warinings, which often cause the simulation to fail. Is there some sort of flag or option i can set, to let spice just ignore nodes that re not connected...
Another question related to this. After running the simulation the display command shows only arrays for voltages and currents in some circuit's branch, however there are no variables for BJT itself like collector current, base current, base-emitter voltage and the like. Does exist a way to include also the above variables as output array for the simulation ? Thanks, Carlo.
Another question related to this. After running the simulation the display command shows only variables for voltages and currents in some circuit's branch, however there are no variables for BJT itself like collector current, base current, base-emitter voltage and the like. Does exist a way to include also the above variables as output array for the simulation ? Thanks, Carlo.
Upgrade to ngspice-42 or edit the model and remove the 'mfg=fairchild' entry. I updated to the version ngspice-42 and it works without removing it ! Thank you.
Upgrade to ngspice-42 or edit the model and remove the 'mfg=fairchild' entry.
I don't think you should ".inc" a ".lib" file. Lib files often want "section" args. Why not ".lib" the library file (with args, if those apply)? Seems like ngspice is trying to evaluate a comment line or something. You need to key on that line (not shown).
Holger thank you for your patience. I didn't see any change in ngspice with [.options reltol=0.0025 vntol=10u abstol=1n] Altering the CLK made all the difference. Unsure why the model/analysis doesn't work for slow CLK. The TI models didn't care if the voltage was 5 versus 3.6 but I redid the 3.6 device to be 3.6 The only other TI behavioral/transient model I could find for a 5V "74C74" device was for the 74HCS74, SN74HCS74.cir. It has the same issues with "slow" CLK as the 74LVC74 device, SN74LVC74A.cir....
Hi, I've a problem loading a circuit that uses a 2N2222 BJT from LTspice standard.bjt lib. The standard.lib file is included in the .cir file using .include directive. Here the error (ngspice-30) Circuit: * c:\users\test\documents\ltspicexvii\carlo\amplificatore-1.asc Original line no.: 9, new internal line no.: 32: Undefined number [fairchild] Original line no.: 9, new internal line no.: 32: Expression err: fairchild)} Original line no.: 9, new internal line no.: 32: Cannot compute substitute Copies=10...
In addition you might have a look at the data sheet, where the supply voltage for this device is limited to a range of 1.65 - 3.6 V. So you are simulating outside of the allowed range, and you can never be sure how the model will react.
Please do not compare apples and oranges. When you do a comparison, please care for exactly the same conditions for both simulators. To achieve the same prerequisites, add this to the ngspice netlist: .options reltol=0.0025 vntol=10u abstol=1n (see LTSPICE --> Tools --> Control Panel) Then run the ngspice example with V1 in 0 DC 0 PULSE( 0 5 10n 10N 10N 90n 200n ) tran 1n 1000n and the simulation is o.k. Try running the example with the slow parameters in LTSPICE PULSE(0 5 100u 10n 10n 1m 2m) .tran...
I tested the TI SN74LVC74A.cir model in LTspice and it worked. ngspice is doing something wrong.
typo
Repeat loop requires plain number, transformed vector, or transformed variable
17.6.2 Repeat - End: loop count requires plain number,
The values of the foreach loop may b given by a vector
17.5.66 Reshape: Alter the dimensionality or dimensions of a vector
The values used in the foreach loop my be given by a vector
Anyway setting the PSPICE compatibility mode works !
Add check for mismatched rparen.
Is it even possible to make the controlled source (E1) value dependent on a simulation -result-? I didn't think it is, certainly not in one step. Now I believe you could stack a vdc (for the "45") and two vcvs for the (1X) V(P,K) and the 95.43*V(G,K) to get the desired outcome and have it work "real-time". But I don't see a way for an attribute to be set by an outcome of what's yet to simulate.
On Windows 7, in which location/folder the spinit or .spiceinit file should be created?
You have to switch on PSPICE compatibility mode by setting set ngbehavior=psa into file spinit or .spiceinit.
Hi, I'm using ngspice-30 to simulate an amplifier with a triode 12AX7A. It is modeled using the following subcircuit: * Connections: Plate * | Grid * | | Cathode * | | | .SUBCKT 12AX7A P G K E1 2 0 VALUE={45+V(P,K)+95.43*V(G,K)} R1 2 0 1.0K Gp P K VALUE={1.147E-6*(PWR(V(2),1.5)+PWRS(V(2),1.5))/2} Cgk G K 1.6P Cgp G P 1.7P Cpk P K 0.46P .ENDS 12AX7A When the circuit is sourced from, I get the following error: ngspice 7 -> source C:\Users\Test\Documents\ngspice\amplificatore-tube-1.cir Circuit: * c:\users\test\documents\ltspicexvii\carlo\amplificatore-tube-1.asc...
The simple answer is no, but it sounds like a nice feature. How would you see it working? My first guess is that Control-Left-Click would zoom in by some ratio around the point of the click, C-R-C would zoom out. Dragging might also be supported. But in the meantime, windows may be closed individually to limit the sprawl (but a keyboard shortcut to close would be nice). An alternative to searching visually may be to use the Measure command to find the interesting event. The manual points out the...
You can plot specific x or y segments. page 404 of manual plot db(v(out)) plot db(v(out)) xlimit 0 20k
Hello! Is there a way to do zooming in the same window? When there is a necessity to find particular detail on plot a lot of windows are created... Thank you in advance.
I noticed one of your KiCad examples "ibis-test" contained a TI 74LVC14 "behavioral" model so I simulated it. When I simulated the 74LVC74A device using the PSpice transient model, the data is wrong. You can compare the data to the MicroCap 74HC74 model. https://www.ti.com/product/SN74LVC74A#design-tools-simulation
I noticed one of your KiCad examples "ibis-test" contained a TI 74LVC14 "behavioral" model. It's hit or miss finding other models however...
Holgers I noticed one of your KiCad examples "ibis-test" contained a TI 74LVC14 "behavioral" model. It's hit or miss finding other models however...
Holgers I noticed one of your KiCad examples "ibis-test" contained a TI 74LVC14 "behavioral" model. I initially had issues because A and Y are "swapped" but it seems to work OK. .SUBCKT SN74LVC14A Y A VCC AGND It's hit or miss finding models however...
Prevent error: implicit declaration of function ‘get_local_home’
add 'option klu' to printout
Holgers I noticed one of your KiCad examples "ibis-test" contained a TI 74LVC14 "behavioral" model. I initially had issues because A and Y are "swapped" but it seems to work OK. .SUBCKT SN74LVC14A Y A VCC AGND Am I oblivious that ngspice has always supported TI's digital behavioral models? I don't know how many TI digital behavioral models are available but it will expand our options. They should be more "accurate" than the MicroCap models. There are also TI digital "transient" models but I haven't...
Holgers I noticed one of your KiCad examples "ibis-test" contained a TI 74LVC14 "behavioral" model. I initially had issues because A and Y are "swapped" but it seems to work OK. .SUBCKT SN74LVC14A Y A VCC AGND Am I oblivious that ngspice has always supported TI's digital behavioral models? Did the recent work to get TI voltage comparator behavioral models to work help? I don't know how many TI digital behavioral models are available but it will expand our options. They should be more "accurate" than...
Holgers I noticed one of your KiCad examples "ibis-test" contained a TI 74LVC14 "behavioral" model. I initially had issues because A and Y are "swapped" but it seems to work OK. .SUBCKT SN74LVC14A Y A VCC AGND Am I oblivious that ngspice has always supported TI's digital behavioral models? Did the recent work to get TI voltage comparator behavioral models to work help? I don't know how many TI digital behavioral models are available but it will expand our options. They should be more "accurate" than...