#40 Vias vs. holes during PCB export to gEDA

[Jiří Čejka]

Hi,

there is one issue when you export newly created PCB from FreeCAD to gEDA. The issue is related to difference between VIA and HOLE like the gEDA handle them.

Now the FreeCAD-PCB exports holes made by sketcher as VIA command which is almost right. The problem is that gEDA has the same command VIA defined in it's PCB file format for both vias (aka plated holes) and holes (aka unplated holes). The difference is only in FLAG used in VIA command to differentiate them to each other. I suppose that using a Sketcher Workbench the user does not compose plated hole (via) but unplated one (hole).

Example what is exported now to gEDA:

Via[44.1781mm -35.2879mm 0mil 20.00mil 0.0000 1.2mm "" ""]

What should be exported:
Via[44.1781mm -35.2879mm 0mil 20.00mil 0.0000 1.2mm "" "hole"]

[Mariusz]

Hello,
fixed.