Open Source Windows Electronic Design Automation (EDA) Software - Page 3

MyHDL is a Python package for using Python as a hardware description and verification language.

Modelio-Open is a project hosting a set of open source extensions (SoaML, SysML and UML Testing Profile) for a previous version (1.2) of the Modelio Free tool . Currently, the lastest version (2.x) of Modelio modeling and generation tool is available at http://modelio.org/downloads/download-modelio.html. All extensions are downloadable at http://forge.modelio.org/projects.

This project is a general AVR bootloader, for different type of AVR device, all you need to do is modify macro definition, and you don not need to modify the main program.

A program by Frederik De Kegel, to control a model rail road with the Intellibox of Uhlenbrock and Modeltreno. Een programma van Frederik De Kegel, om een modeltrein te besturen met de Intellibox van Uhlenbrock en Modeltreno.

PerfDesign is a small application for quickly designing or sketching your own projects on PERFBOARDs and STRIPBOARDs.

DVKit provides an Eclipse-based integrated development environment (IDE) for common design-verification tasks, such as developing SystemVerilog, C++, TCL, Python, and shell code

An automatic 2D Delaunay mesh generator and solver for Finite Element Analysis. Can solve 2D field problems (Poisson and Helmholtz Equations). Can use LAPACK/ARPACK solvers producing OpenGL/Postscript output. Uses C/GTK/GTKGLExt/MFC. Runs on Win32/Unix.

An object-oriented Python Interface to Frontline PCB's Genesis 2000 CAD/CAM/CAE system.

This program provides for easy modification and viewing of SPICE circuit files. It will also read SPICE3 RAW format (as well as GnuCap) and create graphs of results through an interactive GUI. It supports waveform math, copying to clipboard, and saving.

The aim of this project is to develop a GDSII viewer by using Java programming language. Efforts will be made especially on ease-of-use, efficiency, and capacity.

QConsole is a custom Qt widget implementing a standard console to be inherited to support a specific scripting language or shell, and then embedded in any Qt application. As example, a Tcl console (QtclConsole) is provided for use in EDA applications

SimFPGA is a graphical user interface (GUI) tool designed to facilitate the simulation of VHDL projects. It enables users to select VHDL source files and testbenches, configure library and standard settings, and run simulations using GHDL. Additionally, it allows visualization of waveforms through GTKWave. SimFPGA elaborates the project files using GHDL and builds the VHDL project before simulating it. This ensures code verification without the need for additional compilation tools. If an error is detected in any of the project files during elaboration or simulation, a message is displayed in the console indicating the type and location of the error, allowing the user to quickly resolve it.

TimeDoctor is a tool to visualize execution traces of tasks, queues, cache behavior, etc. While originally targeting embedded media processors and includes specific features for analyzing audio/video streaming applications it has wider applicability.

This software is a tool for designing electronic circuits using LaTeX. With an intuitive graphical interface, you can create complex circuits quickly and easily, while the LaTeX code generator translates your designs into code compatible with the LaTeX circuitikz library.

VeriWell is a full Verilog simulator. It supports nearly all of the IEEE1364-1995 standard, as well as PLI 1.0. Yes, VeriWell *is* the same simulator that was sold by Wellspring Solutions in the mid-1990 and was included with the Thomas and Moorby book

Das Field Bus Exchange Format (FIBEX) ist ein XML-Austauschformat für diverse Bussysteme in vernetzten Fahrzeugen. Der Inhalt praxisrelevanter FIBEX-Dateien ist ohne entsprechende Toolunterstützung nur schwer zu fassen. Der FIBEXplorer® bietet einen vielseitigen Viewer für das FIBEX-Format. 100% FIBEX FIBEX Vergleich Linkverfolgung Working Sets Vertikale Navigation Clustered Navigation Startup Wizard By courtesy of Sulzer GmbH (http://www.sulzer.de)

This project provides a analog / mixed signal IC schematic capture and layout tool with the accompanying netlisters, simulators, and verification tools.

Pure Tcl/Tk EDA Package. Schematic capture through to PCB layout. Has Part editor as well as editor for Schematic and PCB Decals.

Tool for store Siemens S7 PLC's data, eg: DB, DI, M and more, in a local file, or write them from local file. Include data editor.

This Python script reads in a DXF (ascii) file and generates a PCB output compatible with PCB Designer, part of the gEDA suite. It is designed for two purposes: One is to generate a PCB snippet from a mechanical drawing (such as a board outline), the other is to produce element files from CAD drawings. PCB snippets are easily imported into an existing gEDA-PCB project using File -> Load Layout to Buffer. Generated element files are ready to use (except for special cases like no-paste flags and rounded pads).

Multiple dielectric transmission line calculator using a 2D field solver to compute the transmission line characteristics from the circuit trace dimensions entered by the user.

bel_fft is a FFT co-processor that can calculate FFTs with arbitrary radix. It is a hardware implementation of the free software Kiss FFT ("Keep it simple, Stupid!"). The target was to allow a simple replacement of the software code with the hardware implementation. Therefore bel_fft comes with a software driver that is compatible with the Kiss FFT routines. bel_fft also has a modular architecture and allows interfacing different bus architectures. So far AMBA AXI, Altera's Avalon bus and the Wishbone bus are supported. However, bel_fft's architecture allows an easy adaptation to further bus architectures (e.g. AMBA AHB). It comes with a Java wizard to configure the co-processor and to generate all required files (e.g. twiddle ROMs). It comes with integration into Xilinx Vivado, EDK, and Altera QSYS and includes example designs for Xilinx Zynq and with PCI-Express core (including Linux driver and application). bel_fft is distributed under the GNU Lesser Public License 2.1.

Ycad is a library of CAD functions in Java. Currently only DXF is supported for reading, viewing and writing. The DXF drawing may be rendered to a Graphics object for printing or imaging.

FSMDesigner is a C++ based implementation for a Finite State Machine (FSM) design tool with integrated Hardware Description Language (HDL) generation. FSMDesigner4 uses the Simple-Moore FSM model guaranteeing efficient fast complex control circuits.

A small Python utility used to manage multiple concurrent installations of Genesis 2000.