Open Source Lazarus Electronic Design Automation (EDA) Software

eLogSim is an event driven, 4-level (0,X,1,Z) digital circuit simulator. It uses a test oriented stimulus approach and offers a statistical (or exhaustive if it makes sense) fault simulation option. eLogSim has a simple GUI and is pre-compiled for Ubuntu 20, Mint 20, CentOS 8, openSUSE 15, FreeBSD 12, Solaris 11, Windows 10/11 & Raspbian/Raspberry PiOS Buster (32/64bit) & Ubuntu-MATE 20.04 (64 bit) operating systems. Cross platform & -network, concurrent fault simulation now available. Commented, easy-to-compile source-code included as well.

ePnR is a simple Integrated Circuit (IC) block standard cell placement & routing tool. ePnR currently supports only circuit blocks using equal height standard cells arranged in one or more channels of user configurable length. Standard cells are described in a simple text based library (compliant with eLogSim). Placement follows initially the cell call order in the SPICE like circuit input netlist. However, a placement optimization, aiming at minimum weighted accumulated wire length, by simulated annealing is available. Routing consists of channel routing as first step. If un-routed connections are left, Maze routing can (optionally) be applied. ePnR does not guarantee completely finished routing. However, un-routed connections will be left with rubberband connections and marked start and end points for subsequent manual routing using a third party layout editor. ePnR outputs in CIF 2.0 and GDS stream format readable by e.g. the free KLayout editor.