Open Source Cygwin Electronic Design Automation (EDA) Software

Ngspice project aims to improve the spice3f5 circuit simulator.

Xschem is a schematic capture program, it allows to create a hierarchical representation of circuits with a top down approach . By focusing on interconnections, hierarchy and properties a complex system (IC) can be described in terms of simpler building blocks. A VHDL, Verilog or Spice netlist can be generated from the drawn schematic, allowing the simulation of the circuit. Key feature of the program is its drawing engine written in C and using directly the Xlib drawing primitives; this gives top speed performance, even on very big circuits. I have succesfully managed to simulate complete VLSI projects with this tool, both digital (Verilog / VHDL) and analog (Spice). Schematics can be printed in SVG, PNG, PDF, formats. XSCHEM runs on Linux or other Unix-likes with Xorg server and on Windows with the Cygwin layer and required tools installed. Can be found also on github: https://github.com/StefanSchippers/xschem

An Electronic Definition Interchange Format (EDIF) parser which allows exports from one EDA schematic capture system (such as OrCad) for import into another (such as KiCad)

A UNIX/X11 circuit drawing application with schematic capture. Features user-definable parts libraries and fully hierarchical SPICE netlist generation.

SmGen is a finite state machine (FSM) generator for Verilog. On the other hand, it is not an FSM entry tool. The input is behavioral Verilog with clock boundaries specifically set by the designer. SmGen unrolls this behavioral code and generates an FSM from it in synthesizable Verilog. Clock boundaries are explicitly provided by the designer so there is good control on the expected timing

TkGate is a event driven digital circuit simulator with a tcl/tk-based graphical editor. TkGate supports a wide range of primitive circuit elements as well as user-defined modules for hierarchical design.

AvrGui jest to program, który zajmuje się kompilacją i programowaniem kontrolerów. Wykorzystuje on kompilator avr-gcc. Zastosowanie biblioteki Qt umożliwia prace programu zarówno na systemach Linux, jak i windows.

ArchC is an open-source architecture description language based on SystemC. Its goal is to provide designers with a tool to evaluate new ideas in processor and ISA design, memory hierarchy, etc. and other aspects of computer architecture research.

Capsim(r) C Text Mode Kernel(TMK),DSP and communication blocks, topologies, libraries and tools for the development of high performance block diagram digital signal processing and communications systems,built in interpreter for scripting.SystemC support.

"kdiv" is a generator of routines for optimized division by an integer constant based on the work presented in H.S. Warren's "Hacker's Delight". "kdiv" can be used to emit a generic assembly or C implementation of (signed/unsigned) division.

FPGAsm is a low-level alternative to verilog and VHDL. A near-instant 'assembler for FPGAs', this simple yet powerful language facilitates bottom-up design, layout and wiring of modules, and generation of .xdl output. With about 10 keywords to learn, you can start making circuits in minutes. Now you can focus on learning the ins and outs of the FPGA instead of complex tools and languages. Fast turnaround time and bottom-up approach invite exploration, experimentation, live circuit testing and physical test harness creation, radically changing the workflow. FPGAsm offers you an opportunity to REALLY understand Xilinx FPGAs, create circuits DIRECTLY on the FPGA using an opensource tool, and share your knowlege and projects with the community. Supported architectures: Xilinx (via xdl)

Now you can translate your vectorial and bitmap design data to your CNC machines! OpenCAM provides an interface where you can configure your CNC equipment and then export the file followiing it's commands! You can export PS,PDF,AI,EPS,DXF,SVG and Bitmap

Proyecto fin de carrera de Daniel Gaviño

PKtool is a SystemC/C++ environment dedicated to the power estimation for digital systems described in SystemC.

HW(VHDL) and SW of logic analyzer and On-Chip-Verification(OCV) for Value Change Dump(VCD) file format that exported to seemd SystemC ,ModelSIM, and many other EDA tools. Very easy and Simple.

PEP is a modelling and verification framework for parallel systems, providing a large number of different modelling languages and verification techniques (e.g. SDL, Petri nets and model checking)

Brushless DC controller (ESC) Fully functional sensorless ESC. Uses BEMF detecton for rotor position sensing. Software trays to maintain maximum speed on currently available power(pwm duty). It works like ordinary DC motor. More load means, on same power, lower speed and higer current. Motor speed (current) PWM , direction etc. is adjustable via serial port commands. For example - press "k" button to add power, "j" button to reduce power and "t" button to reverse rotor direction etc. I have used neodymium magnets BLDC, CD drive BLDC and car generator as BLDC motor without any modification in software, hardware - it just works. Schematic is done using EAGLE PCB software Software is witten in spin langue. If You want to improve this project then put your thoughts into discussion section. Or if You have some burning information - drop me an email "htamme@ut.ee" enjoy,

"mprfgen" is a multi-port memory generator that can be used for VHDL designs. It can generate either generic or Xilinx-specific (through component instantiation) multi-port memories.

YAPI (Y-chart Application Programmers' Interface aka Yet Another Programmers' Interface) is a C++ library for writing (Kahn) Process Networks.