ipf-orc-support Mailing List for Open Research Compiler - Aurora

  hi,
  	i want to build cross compiler and the links for NUE suite are
  expired ...

can someone update the page or let me know if there is another alternative
  or provide me the url of a working link..

  any kind of help will be greatly appreciated..

  thanks for your time ..

  Pramodh.


-- 
 	be who you are and say what you feel because those who mind
 	doesn't matter and those who matter don't mind.

Hello,

I'm trying to insert a call to a function (in a library) into the  
WHIRL Tree.  I've traversed the tree, identified where I want to  
insert the node, created entries in the symbol table and the type  
table, and created the node. However, when I try to print that node  
to the screen (i.e.. using fdump_tree() or fdump_tree_no_st() ) the  
compiler seg faults. Does anyone know what the problem may be?


Here's some code if it helps (kinda based off of code from be/lno/ 
mem_sim.cxx):

...
ST *func = Create_ST_For_VCALL();
WN *wn_new = WN_Call(MTYPE_V , MTYPE_V, 0, func );
WN_INSERT_BlockAfter( parent_block, first_kid, wn_new);
fdump_tree_no_st(stdout, wn_new);
...

static ST *Create_ST_For_VCALL()
{
   ST *result=NULL;
    TY_IDX new_ty;

     char* name = "test_func";

    STR_IDX func_name = Save_Str(name);
    TY_IDX  func_ty = Make_Function_Type( MTYPE_To_TY( MTYPE_V ) );
    Set_TY_has_prototype(func_ty);
    TY_IDX ty_func_ret_idx = Make_Pointer_Type (Be_Type_Tbl(MTYPE_V));
    TY *voidpty = &(Ty_Table[ty_func_ret_idx]);

    TY_Init(Ty_Table[func_ty], TY_size(ty_func_ret_idx),  
KIND_FUNCTION, MTYPE_V,
func_name );

    Enter_TY (func_ty);

    /* Make a ST: add function to global symbol table */
    result = New_ST ( TRUE );
    ST_Init(result, func_name, CLASS_FUNC, SCLASS_EXTERN,  
EXPORT_PREEMPTIBLE,func
_ty);

Enter_ST ( result);
   return result;
}


Thanks,
Stephen Curial

M.Sc. Student
University of Alberta
http://www.cs.ualberta.ca/~curial/

See the code in Configure_Prefetch in cgdriver.cxx

if ( ! CG_enable_pf_L1_ld_overridden ) CG_enable_pf_L1_ld = FALSE; if ( !
CG_enable_pf_L1_st_overridden ) CG_enable_pf_L1_st = FALSE;

That will prohibit the back end to generate prefetch instruction for level
1 cache.

Why?

In the other hand, Pathscale 2.1 did alter the code to enable L1 prefetch
in backend, but it is for X86-64 not for IA64.

I want to know how many times each function is called given a executable
file by orcc.
 
In detail,  I want to know each call's call site as well as its caller. 
  
Using gcc,  instrumentation of each function call can be done using
"-finstrument-functions" option. 
   
Does anybody know similar and/or another way? 
    
     
--Yoonseo

---------- Forwarded message ----------
From: Yoonseo Choi <yoo...@gm...>
Date: Oct 18, 2005 9:07 PM
Subject: function instrumentation
To: ipf...@so...

 I want to know how many times each function is called given a executable
file by orcc.
 In detail, I want to know each call's call site as well as its caller.
 Using gcc, instrumentation of each function call can be done using
"-finstrument-functions" option.
 Does anybody know similar and/or another way?
  --Yoonseo

The answer is YES. MII computation will take care of parallelism, and
non-constant counted loop can be handled by br.ctop instruction.

--=20
Jason
=20

-----Original Message-----
From: ipf...@li...
[mailto:ipf...@li...] On Behalf Of
U.Ramakrishna
Sent: Tuesday, May 24, 2005 7:03 AM
To: ipf...@li...
Cc: Lakshmi Renganarayana
Subject: [Ipf-orc-support] SWP of loops with non-constant loop bounds

Hello,

We have a few questions on the working of software pipeliner (SWP)
of ORC (for IA-64) on loops whose bounds are not constant.

Consider the following simple loop nest

for (i =3D 1; i < N ; i++)
    for(j =3D 1; j < N; j++)
	A[i,j] =3D A[i-1,j] + A[i,j-1];

After skewing and permutation we get the following transformed loop nest

for (j =3D 2; j < N + N ; j++)
    for(i =3D MAX(1,j-N); i < MIN(N,j-1); i++)
	A[i,j-i] =3D A[i-1,j-i] + A[i,j-i-1];


In the transformed loop nest,
1. all the iterations of the inner (i) loop are parallel
2. the bounds of the i loop are not constant.

Can the software pipeliner in ORC detect and exploit this parallelism,
i.e., the parallelism across the iterations of the inner most loop of
the transformed loop nest?

If not, what kind of transformation will make the software pipeliner
exploit this inter-iteration parallelism? For example, will converting
the inner most loop to a while loop help?

Any help/suggestions would be appreciated.

Thanks and Regards
Ramakrishna
Lakshminarayanan


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Hello,

We have a few questions on the working of software pipeliner (SWP)
of ORC (for IA-64) on loops whose bounds are not constant.

Consider the following simple loop nest

for (i = 1; i < N ; i++)
    for(j = 1; j < N; j++)
	A[i,j] = A[i-1,j] + A[i,j-1];

After skewing and permutation we get the following transformed loop nest

for (j = 2; j < N + N ; j++)
    for(i = MAX(1,j-N); i < MIN(N,j-1); i++)
	A[i,j-i] = A[i-1,j-i] + A[i,j-i-1];


In the transformed loop nest,
1. all the iterations of the inner (i) loop are parallel
2. the bounds of the i loop are not constant.

Can the software pipeliner in ORC detect and exploit this parallelism,
i.e., the parallelism across the iterations of the inner most loop of
the transformed loop nest?

If not, what kind of transformation will make the software pipeliner
exploit this inter-iteration parallelism? For example, will converting
the inner most loop to a while loop help?

Any help/suggestions would be appreciated.

Thanks and Regards
Ramakrishna
Lakshminarayanan

I have discovered a seg fault bug in ipa-link when building the spec 
benchmark 255.vortex.  However, I don't really know what the seg-faulting 
code is doing, and there isn't anything obviously wrong or any sort of 
trivial fix.

The seg-fault is repeatable, in both the debug and normal native builds of 
the ORC.  I've included the gdb backtrace below, and will assist in 
any way I can if anyone wanted to look into this problem.

--Paul

-----

Program received signal SIGSEGV, Segmentation fault.
WN_opcode (wn=0x0) at ../../common/com/wn_core.h:884
884                               wn->common.desc);
Current language:  auto; currently c++
(gdb) where
#0  WN_opcode (wn=0x0) at ../../common/com/wn_core.h:884
#1  0x20000000005ed550 in IPO_INLINE::Process_Callee 
(this=0x60000fffffffa640, aux=@0x60000fffffffa490, same_file=0)
    at ../../ipa/main/optimize/ipo_inline.cxx:3191
#2  0x20000000005ee8d0 in IPO_INLINE::Process (this=0x60000fffffffa640) at 
../../ipa/main/optimize/ipo_inline.cxx:3347
#3  0x20000000005b2f00 in Inline_Call (caller=0x60000000004e0ea0, 
callee=0x6000000000240188, edge=0x6000000000577378, 
    cg=0x60000000002495e0) at ../../ipa/main/optimize/ipo_main.cxx:344
#4  0x20000000005b47d0 in IPO_Process_edge (caller=0x60000000004e0ea0, 
callee=0x6000000000240188, 
    edge=0x6000000000577378, cg=0x60000000002495e0) at 
../../ipa/main/optimize/ipo_main.cxx:558
#5  0x20000000005b5230 in Perform_Transformation 
(caller=0x60000000004e0ea0, cg=0x60000000002495e0)
    at ../../ipa/main/optimize/ipo_main.cxx:668
#6  0x20000000005bdb40 in IPO_main (cg=0x60000000002495e0) at 
../../ipa/main/optimize/ipo_main.cxx:1344
#7  0x20000000005bfc60 in Perform_Interprocedural_Optimization () at 
../../ipa/main/optimize/ipo_main.cxx:1610
#8  0x20000000004715f0 in ipa_driver (argc=6, argv=0x600000000001c470) at 
../../ipa/common/ipc_main.cxx:191
#9  0x40000000000320f0 in main (argc=93, argv=0x60000fffffffac78, 
envp=0x600000000000f8a8)
    at ../../cygnus_20000828/ld/ldmain.c:381

Paul,

ORC will produce different binaries for Itanium1 and Itanium2 because =
they have different hardware resources and constraints.
On ORC2.1, the default target is Itanium2. To switch the target machine, =
you should add the option "-itanium" on the commond line.=20

Lixia Liu
-----Original Message-----
From: ipf...@li... =
[mailto:ipf...@li...] On Behalf Of Paul =
Berube
Sent: 2005=C4=EA5=D4=C24=C8=D5 3:41
To: ipf...@li...
Subject: [Ipf-orc-support] Itanium-1 vs Itanium-2 with ORC


Hi,

I've been doing my work so far on an Itanium-2 machine, but I have just=20
aquired some time on some Itanium-1 machines.  I'd rather not have to=20
build and install my modified ORC in the new environment, so I had a few =

questsion:

- Are binaries produced by the ORC identical for Itanium-1 and =
Itanium-2?
- If not, if I wanted to cross-compile, what flag would I give the ORC =
to=20
  specify an Itanium-1 target machine?

Thanks.
--Paul



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Hi,

I've been doing my work so far on an Itanium-2 machine, but I have just 
aquired some time on some Itanium-1 machines.  I'd rather not have to 
build and install my modified ORC in the new environment, so I had a few 
questsion:

- Are binaries produced by the ORC identical for Itanium-1 and Itanium-2?
- If not, if I wanted to cross-compile, what flag would I give the ORC to 
  specify an Itanium-1 target machine?

Thanks.
--Paul

Paul Berube wrote:

> Sorry this is off-topic, but you're the people I know who know about the 
> Itanium.

Several IPF gurus follow the Gelato-technical mailing list.
https://www.gelato.unsw.edu.au/mailman/listinfo/gelato-technical

> "GAP 4 on Itanium is a problem at present. Paul, if you know how to locate 
>  the top and bottom of the "second stack" on an Itanium (the one used for 
>  register window overflows) from C code, ideally in a non compiler 
>  specific way, I'd be interested."

http://www.intel.com/design/itanium/manuals/245318.pdf
Refer to Chapter 6 in Part I (Register Stack Engine)

<quote>
As shown in Figure 6-1, the backing store is organized as a stack in 
memory that grows from lower to higher addresses. The Backing Store 
Pointer (BSP) application register contains the address of the first 
(lowest) memory location reserved for the current frame (i.e., the 
location at which GR32 of the current frame will be spilled). RSE 
spill/fill activity occurs at addresses below what is contained in the 
BSP since the RSE spills/fills the frames of the current procedure's 
parents. The BSPSTORE application register contains the address at which 
the next RSE spill will occur. The address register which corresponds to 
the next RSE fill operation, the BSP load pointer, is not 
architecturally visible. The addresses contained in BSP and BSPSTORE are 
always aligned to an 8-byte boundary. The backing store contains the 
local area of each frame. The output area is not spilled to the backing 
store (unless it later becomes part of a callee's local area). Within 
each stack frame, lower-addressed registers are stored at lower memory 
addresses.
</quote>

Application registers of interest are AR16, AR17, and AR18.

See Volume 1 - Part I - Section 3.1.8 for more details.

> My first impression is that you can't find that stack using just C code, 
> but maybe someone knows some kind of trick?

You need assembly code to read the application registers.

e.g.
mov r8 = ar17 ;;
mov r9 = ar18 ;; /* SIGILL if ar[RSC].mode != 0 */

-- 
Regards, Marc

Sorry this is off-topic, but you're the people I know who know about the 
Itanium.

The people over at gap-system.org are helping me with the 254.gap 
benchmark from SPEC CINT2000.  Turns out they have an Itanium problem, so 
I said I'd see what I could find out...  If you have any information 
related to this question, please let me know and I'll collect and forward 
the responses.

"GAP 4 on Itanium is a problem at present. Paul, if you know how to locate 
 the top and bottom of the "second stack" on an Itanium (the one used for 
 register window overflows) from C code, ideally in a non compiler 
 specific way, I'd be interested."

My first impression is that you can't find that stack using just C code, 
but maybe someone knows some kind of trick?

On Mon, 28 Mar 2005, U.Ramakrishna wrote:

> I have done some transformations manually on an input C file
> (specific to tiling) and want to observe how those changes interact with
> the software pipelining stage of ORC.
> 
> I know that the code to print the debug information is in the
> file .../osprey1.0/be/cg_swp.cxx (and other related files too).

As the last guy to be asking this sort of thing, let me try to pass on 
what I've learned:

First, the how_to_debug_compiler file in the docs directory has some 
useful info.

Now, I assume you are looking at something guarded by an 
if(Get_Trace(TP_SWPIPE, <num>)... these are indeed key to turning on your 
desired output.

TP_SWPIPE is the phase number, as defined in common/util/tracing.[c,h].  
In this case, TP_SWPIPE is defined as 50.

We also need a particular tracing flag for the phase, that would be 
whatever goes where <num> is above.  Usually these are defined constants 
in some .h file related to the phase... but with SWPIPE it looks like 
there are just numeric constants in the code (ick!).  So, for example, on 
line 144, there is 

Get_Trace(TP_SWPIPE, 2)

so the phase-specific tracing flag is 2 (I have no idea what 2 is for, 
since there is no name for it :(  )

Now, to use this info:

-Wb,-tt50:0x0002
  ^   ^       ^
  |   |       phase-specific tracing flag value
  |   ------- phase to trace
  ----------- Wj is whirl level, Wb is the back end

Since it looks like SWPIPE is in the back end (based on what I see in 
tracing.h), you'll want -Wb, not -Wj.

If you figure out some of the phase-specific tracing flags for SWPIPE, 
mail them to me, as I'm putting together a friendlier reference for the 
flags, as I find and use them myself. Not much there yet, but you can 
see it here:
http://www/cs.ualberta.ca/~berube/orc/phases.shtml

As you can see, there is only any info for the if-conversion phase, and 
not even all the main phases are there yet, but it'll get there...

As a side note, you can add your own phase-specific flags to customize 
your tracing by simply defining _new_ phase-specific flags (note, don't 
overlap any bits already in use.  check out the if-conversion flags for a 
clean example), and passing them in the same way.

Hope that helps!
--Paul

Hello,
Apologies if this is too naive.

I have done some transformations manually on an input C file
(specific to tiling) and want to observe how those changes interact with
the software pipelining stage of ORC.

I know that the code to print the debug information is in the
file .../osprey1.0/be/cg_swp.cxx (and other related files too).

My question is, about printing the information in the file.
for example, if I want to print the ResMII for an arbitrary .c file

There seem to be some compiler flag which when enabled can print the
software pipelining statistics. What are the flags and how can they be
enabled. This seem to have been asked before, in the mailing lists,
but i could not find any answers.

So some examples or even a link to some documentation as to
how to do it would be very appreciated.

Thanks
Ramakrishna

Hello,

I was trying to build the debuggable whirl2c program without having to use the Backend executable
(be). There is a program called whirl2.c in the whirl2c directory which seemed to do exactly that.
Although at first it didn't compile, I managed to build it (changing it to a .cxx program) and
doing some small changes. 

Program is roughly this (but please see attachments):

=========================================
      (void)Open_Input_Info(Irb_File_Name);
      
      Initialize_Symbol_Tables(FALSE);
      New_Scope(GLOBAL_SYMTAB, Malloc_Mem_Pool, FALSE);      

      pu_tree = Read_Global_Info(NULL);
      W2C_Process_Command_Line(argc, argv, argc, argv);
      
      W2C_Outfile_Init(TRUE);
      
      /* Loop thru all the PUs */
      for (current_pu = pu_tree;
	   current_pu != NULL;
	   current_pu = PU_Info_next (current_pu)) {

	 Current_PU_Info = current_pu;
	 MEM_POOL_Push (MEM_pu_nz_pool_ptr);
	 Read_Local_Info (MEM_pu_nz_pool_ptr, current_pu);
	 pu = PU_Info_tree_ptr(current_pu);

	 W2C_Outfile_Translate_Pu(pu, TRUE/*emit_global_decls*/);
	 
	 if (PU_Info_child(current_pu)) {
	    fprintf(stderr, "WARNING: ignoring nested procedures in \"%s\"\n",
		    ST_name(PU_Info_proc_sym(current_pu)));
	 }

	 Free_Local_Info (current_pu);
	 MEM_POOL_Pop (MEM_pu_nz_pool_ptr);
      } /* for each PU */

      W2C_Outfile_Fini(TRUE);
      Cleanup_Files(TRUE, FALSE);
   }

=========================================

Now the program is running but there is still a problem. It produces a segmentation fault (core
dump):

=========================================
Program received signal SIGSEGV, Segmentation fault.
0x4002ffc5 in Accumulate_Expr_PUinfo (root=0x4056a260) at ../../be/whirl2c/PUinfo.cxx:1079
1079                   Is_True(CALLSITE_call(last_callsite) == wn,
(gdb) print last_callsite
$1 = (CALLSITE *) 0x0
(gdb) bt
#0  0x4002ffc5 in Accumulate_Expr_PUinfo (root=0x4056a260) at ../../be/whirl2c/PUinfo.cxx:1079
#1  0x4003033c in PUinfo_init_pu (pu=0x4056a1b8, body_part_of_interest=0x4056a260) at
../../be/whirl2c/PUinfo.cxx:1195
#2  0x40040693 in W2C_Push_PU (pu=0x4056a1b8, body_part_of_interest=0x4056a260) at
../../be/whirl2c/w2c_driver.cxx:758
#3  0x40041606 in W2C_Outfile_Translate_Pu (pu=0x4056a1b8, emit_global_decls=1) at
../../be/whirl2c/w2c_driver.cxx:1259
#4  0x08049a14 in main (argc=3, argv=0xbffff334, envp=0xbffff344) at
../../be/whirl2c/whirl2c.cxx:392
=========================================

If I use the normal whirl2c with the same input file, the execution proceeds normally

Can anyone please give me some advice on how to solve this?

Thanks and regards,


		
__________________________________ 
Do you Yahoo!? 
Make Yahoo! your home page 
http://www.yahoo.com/r/hs

Hi,

There is a file called whirl_view for displaying WHIRL trees using DaVinci I think. Which flag
controls the generation of this information? Is an output file produced that can be loaded with
Davinci?

Also, what is the flag for generating .N whirl intermediate files?

Thanks


		
__________________________________ 
Do you Yahoo!? 
Yahoo! Small Business - Try our new resources site!
http://smallbusiness.yahoo.com/resources/ 

On Wed, Mar 16, 2005 at 09:56:18AM +0100, Marc Gonzalez-Sigler wrote:

> All of these functions (except swapINX and swapRM) are also exported
> by GNU's libm. Is the SGI implementation supposed to be more optimized?

Those functions aren't that fast on x86.

> What is libmv.a? When are the functions exported by libmv called,
> only in Fortran code?

Vector versions of the math functions. It is used from all languages.

-- greg

I have several questions for those familiar with libmsgi, libmv, and the
osprey1.0/libm directory.

libmsgi.a is built when BUILD_VARIANT != LIBMV

libmsgi.a exports the following functions:
acos
acosf
asin
asinf
atan
atan2
atan2f
atan2l
atanf
cabs
cabsf
ceil
ceilf
copysign
cos
cosf
cosh
coshf
drem
erf
erfc
exp
expf
expm1
expm1f
fabs
fabsf
finite
floor
floorf
fmod
fmodf
fsqrt
gamma
hypot
hypotf
j0
j1
jn
lgamma
log
log10
log10f
log1p
log1pf
logb
logf
pow
powf
remainder
rint
sin
sinf
sinh
sinhf
sqrt
sqrtf
swapINX
swapRM
tan
tanf
tanh
tanhf
trunc
truncf
y0
y1
yn

All of these functions (except swapINX and swapRM) are also exported
by GNU's libm. Is the SGI implementation supposed to be more optimized?

What are common.exports, libmx.exports, and mips3.exports? I note
common.exports is used when building libinstr. Are they used to
specify which symbols should be exported, like ld version scripts?

libmv.a is built when BUILD_VARIANT == LIBMV

What is libmv.a? When are the functions exported by libmv called,
only in Fortran code?

-- 
Regards, Marc

Hi,

I'm working in the if-converter, and need to know the bigger compilation 
context.  In particular, in 

be/cg/orc_intel/if_conv.cxx:IF_CONVERTOR::Worth_If_Convert

I'd like to know the current file name, pu name, and unique idenfication 
numbers for these, if they exist.  Something like 	    

ST_name(PU_Info_proc_sym(current_pu)) and 
Current_PU_Count())

from be/be/driver.cxx, for example, although these won't work since I 
can't seem to find any reference to the current pu in the scope of 
Worth_If_Convert.

Thanks for any suggestions!

On Wed, 23 Feb 2005, Chunhua Liao wrote:

> osprey1.0/doc/howto-debug-compiler 
> The command is like " orcc -flag1  -Wb, -ttPhase:flags x.c "
> Find all phase names in common/util/tracing.c .h

Great, this is exactly what I needed to know.

Thanks!


> Chunhua Liao
> -----Original Message-----
> From: ipf...@li...
> [mailto:ipf...@li...] On Behalf Of Paul
> Berube
> Sent: Wednesday, February 23, 2005 4:57 PM
> To: ipf...@li...
> Cc: Peng Zhao
> Subject: [Ipf-orc-support] Easy question on command line flags
> 
> 
> Hi, this seems like a really easy thing, but I can't seem to figure it
> out... I want to enable LNO_Verbose, which is set by:
> 
> LNO_Verbose = Get_Trace(TP_LNOPT, TT_LNO_VERBOSE);
> 
> I found that TT_LNO_VERBOSE is defined:
> 
> #define  TT_LNO_VERBOSE                        0x00000004 
> 
> and that there is a -LNO:: option group for command line parameters.
> 
> 
> I have a feeling that I have all the info I need to turn LNO_Verbose on... 
> I just don't understand how to create the appropriate command line flag to
> make the magic happen :(
> 
> If someone could tell me the proper flag, that would be good.
> 
> If someone could tell me how to come up with the proper flag on my own so I
> don't have to ask next time, that would be even better! :)
> 
> Thanks!
> 
> 
> 
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> 
> 
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> 

Paul Berube wrote:

> Andrey Chaltsev wrote:
> 
>> Is there any possibility to install and run ORC cross compiler without NUE?
> 
> As I understand it, NUE is only a IA-64 simulator, and only required if you
> want to run the IA64 binaries produced by the ORC on an IA-32 machine. Note
> that the ORC _only_ produces IA-64 binaries.
> 
> The cross compiler will allow you to build the ORC so the ORC runs on IA-32,
> but produces IA-64 binaries.  You'll need to have access to an IA-64 machine
> to actually run the programs, or you'll need and IA-64 simulator like NUE.
> 
> I believe you should be able to build (and probably install, though I always
> build from source) the ORC cross compiler without NUE (make.cross), just skip
> all the nue-related instruction.  In particular, be sure _not_ to skip
> setting the env. vars, in particular COMP_TARGET_ROOT.
> 
> I'm pretty sure I've done this and it worked... but I've tried a lot of
> things and I may be confused.  Hopefully someone with more experience and
> expertise will correct me if I'm wrong...

Paul,

I think you have Ski and NUE mixed up.

http://web.archive.org/web/2003/www.software.hp.com/products/LIA64/overview2a.htm

"While it is possible to use Ski in a standalone fashion, we recommend that it 
be used in conjunction with the Native User Environment (NUE) that is also being 
distributed along with Ski. NUE runs on Linux-based IA-32 computers and emulates 
an IA-64 Linux environment. A user executing NUE will be in an environment that 
largely behaves as if the user were running on an IA-64 system.

NUE provides the toolchain (compiler, linker, assembler), the libraries, and 
execution environment necessary to develop IA-64 Linux software. A user running 
within NUE can compile, link and execute applications as if he or she were on an 
IA-64 system executing the Linux operating system."

http://www.hpl.hp.com/research/linux/ski/nue-info.php

"NUE was built entirely based on open-source software. It was basically just a 
chroot'ed environment in which the compiler and linkers were i386-to-ia64 
cross-tools and the ia64-versions of the header-files and libraries were 
installed in the standard locations (e.g., /usr/include and /usr/lib)."

The ORC distribution provides its own cross-assembler and cross-linker (*)
but it still requires IA-64 GCC-2.96-compatible headers. These are provided
by NUE, but they can also be installed manually.

(*) See orc-2.1/bin/ia32-linux/util

-- 
Regards, Marc

On Wed, 23 Feb 2005, Andrey Chaltsev wrote:
> 
> I have tried to install ORC compiler (orc-2.1) on not IA-64 machine.
> As I understand from 
> http://ipf-orc.sourceforge.net/readme-release-2.1.htm,
> to do this it is necessary to install NUE.
> The problem is that NUE does not exist any more.
> (Look at http://www.hpl.hp.com/research/linux/ski/nue-info.php)
> 
> Is there any possibility to install and run ORC cross compiler without 
> NUE?

As I understand it, NUE is only a IA-64 simulator, and only required if 
you want to run the IA64 binaries produced by the ORC on an IA-32 machine.  
Note that the ORC _only_ produces IA-64 binaries.

The cross compiler will allow you to build the ORC so the ORC runs on 
IA-32, but produces IA-64 binaries.  You'll need to have access to an 
IA-64 machine to actually run the programs, or you'll need and IA-64 
simulator like NUE.

I believe you should be able to build (and probably install, though I 
always build from source) the ORC cross compiler without nue 
(make.cross), just skip all the nue-related instruction.  In particular, 
be sure _not_ to skip setting the env. vars, in particular 
COMP_TARGET_ROOT.

I'm pretty sure I've done this and it worked... but I've tried a lot of 
things and I may be confused.  Hopefully someone with more experience and 
expertise will correct me if I'm wrong...

Good Luck!
--Paul

There is a document for how to use tracing flags:

osprey1.0/doc/howto-debug-compiler 

The command is like " orcc -flag1  -Wb, -ttPhase:flags x.c "
-flag1 insures the component you want to trace will be actually activated.

Find all phase names in common/util/tracing.c .h
Tracing flags are scattered in individual subdirectories for each
components. For example: 
be/lno/lnopt_main.h  defines flags for LNO phase

Good luck.

Chunhua Liao
-----Original Message-----
From: ipf...@li...
[mailto:ipf...@li...] On Behalf Of Paul
Berube
Sent: Wednesday, February 23, 2005 4:57 PM
To: ipf...@li...
Cc: Peng Zhao
Subject: [Ipf-orc-support] Easy question on command line flags


Hi, this seems like a really easy thing, but I can't seem to figure it
out... I want to enable LNO_Verbose, which is set by:

LNO_Verbose = Get_Trace(TP_LNOPT, TT_LNO_VERBOSE);

I found that TT_LNO_VERBOSE is defined:

#define  TT_LNO_VERBOSE                        0x00000004 

and that there is a -LNO:: option group for command line parameters.


I have a feeling that I have all the info I need to turn LNO_Verbose on... 
I just don't understand how to create the appropriate command line flag to
make the magic happen :(

If someone could tell me the proper flag, that would be good.

If someone could tell me how to come up with the proper flag on my own so I
don't have to ask next time, that would be even better! :)

Thanks!



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ipf-orc-support mailing list
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Hi, this seems like a really easy thing, but I can't seem to figure it 
out... I want to enable LNO_Verbose, which is set by:

LNO_Verbose = Get_Trace(TP_LNOPT, TT_LNO_VERBOSE);

I found that TT_LNO_VERBOSE is defined:

#define  TT_LNO_VERBOSE                        0x00000004 

and that there is a -LNO:: option group for command line parameters.


I have a feeling that I have all the info I need to turn LNO_Verbose on... 
I just don't understand how to create the appropriate command line flag to 
make the magic happen :(

If someone could tell me the proper flag, that would be good.

If someone could tell me how to come up with the proper flag on my own so 
I don't have to ask next time, that would be even better! :)

Thanks!

Hello

I have tried to install ORC compiler (orc-2.1) on not IA-64 machine.
As I understand from 
http://ipf-orc.sourceforge.net/readme-release-2.1.htm,
to do this it is necessary to install NUE.
The problem is that NUE does not exist any more.
(Look at http://www.hpl.hp.com/research/linux/ski/nue-info.php)

Is there any possibility to install and run ORC cross compiler without 
NUE?


           Andrey Chaltsev
                                   Feb 23

           E-mail:      a.c...@cs...
           Address:     room 2.70, Computer Science Department,
                        The University of Manchester,
                        Kilburn Building, Oxford Road,
                        Manchester, M13 9PL, UK